1. Field of the Invention
This present invention relates to a data processor which is capable of executing such two kinds of instructions as a first, kind of instruction and a second kind of operation instruction which is capable of being executed independently from the first kind of instruction, such as a data processor comprising the mechanism of integer operation and the mechanism of floating-point operation, and more in particular, to a data processor which is capable of effectively processing an exception which was generated when either of the two kinds of instructions, such as the floating-point operation instruction, was executed.
2. Description of Related Art
The conventional data processor is constructed to sequentially execute instructions, however, since processing speed of the data processor has been highered, there is proposed a data processor whose performance is greatly improved by providing pipeline processing for the instructions.
Such a data processor which provides pipeline processing for the instructions is disclosed in detail in U.S. Pat. No. 4,402,042 or Japanese Patent Application Laid-Open No. 63-193230 (1988) and the like, for example.
In addition to it, there is proposed a data processor which packages such two kinds of operation functions as a floating-point operation function and an integer operation function onto one semiconductor chip and performs parallel execution of an integer operation instruction and a floating-point operation instruction in order to improve processing performance of the data processor.
Such a data processor as performs parallel execution of the integer operation and the floating-point operation is disclosed in detail in Leslie Kohn and Sai-Wai Fu, "A 1,000,000 Transistor Microprocessor", 1989 ISSCC Digest of Papers, pp.54-55, for example.
Incidentally, it takes longer time to execute the floating-point operation than to execute the integer operation. As a result, where the integer operation instruction and the floating-point operation instruction are executed simultaneously by allowing an integer operation unit and a floating-point operation unit to perform parallel operation, there exists a problem that at what time point an exception which was generated when a floating-point operation instruction was executed is to be accepted. In other words, until the exception which was generated when the floating-point operation instruction was executed is detected, there is possibility that execution of several integer operation instructions which are described on the latter order of a program will be terminated earlier than execution of that floating-point operation instruction because of the difference of processing speed between the floating-point operation and the integer operation.
As a result, where the exception which was generated when the floating-point operation instruction was executed is adapted to be accepted surely before execution of the next floating-point operation instruction, it becomes necessary to check whether the exception which was generated when the floating-point operation instruction was executed is generated or not, at every time the floating-point operation is executed, which becoming an obstacle to improve performance of the data processor.
In order to avoid such inconvenience as described above, conventionally there has been proposed a data processor, wherein the exception which was generated when the floating-point operation instruction was executed is either accepted to be delayed until just before execution of the next floating-point operation instruction or accepted as external interruption.
Such a data processor, which is constructed to perform switching of mode that the exception which was generated when the floating-point operation instruction was executed is either accepted to be delayed until just before execution of the next floating-point operation instruction or accepted as external interruption, is disclosed in detail in "i486 MICROPROCESSOR Intel Corporation 1989", for example.
Where many instructions are executed after an exception was generated and then the exception is detected, however, it becomes difficult to specify the reason why the exception was generated. Then, where the exception is accepted before execution of the next floating-point operation instruction, it becomes an obstacle to improve performance of the data processor, however, where an exception is generated when a floating-point operation instruction is executed, it is convenient to detect the exception as soon as possible in processing of the exception.
On the contrary, where the exception generated when the floating-point operation instruction was executed is accepted to be delayed until just before execution of the next floating-point operation instruction, many integer operation instructions, jump instructions, and the like are executed during that time, then, it becomes difficult to specify address of the floating-point operation instruction which generated the exception or the reason why the exception was generated.
With the conventional data processor, such as i486 microprocessor manufactured by Intel Corp., delaying time from generating an exception to detecting the exception is adapted to be reduced by accepting the exception which was generated when the floating-point operation instruction was executed as external interruption, as a result, there exists a problem to additionally entail a signal pin for outputting the exception generated when the floating-point operation instruction was executed to the external. In addition, there is another problem to entail in the external of the microprocessor a control circuit which arbitrates signals showing both of other external interruption and the exception generated in execution of the floating-point operation instruction.